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Wenzel Jakob
104 lines
4.0 KiB
C++
104 lines
4.0 KiB
C++
/*
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Copyright 2005-2016 Intel Corporation. All Rights Reserved.
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This file is part of Threading Building Blocks. Threading Building Blocks is free software;
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you can redistribute it and/or modify it under the terms of the GNU General Public License
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version 2 as published by the Free Software Foundation. Threading Building Blocks is
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distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the
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implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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See the GNU General Public License for more details. You should have received a copy of
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the GNU General Public License along with Threading Building Blocks; if not, write to the
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Free Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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As a special exception, you may use this file as part of a free software library without
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restriction. Specifically, if other files instantiate templates or use macros or inline
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functions from this file, or you compile this file and link it with other files to produce
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an executable, this file does not by itself cause the resulting executable to be covered
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by the GNU General Public License. This exception does not however invalidate any other
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reasons why the executable file might be covered by the GNU General Public License.
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*/
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#ifndef __TBBexample_graph_logicsim_oba_H
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#define __TBBexample_graph_logicsim_oba_H 1
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namespace P {
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//input ports
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const int CI = 0;
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const int A0 = 1;
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const int B0 = 2;
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const int A1 = 3;
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const int B1 = 4;
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const int A2 = 5;
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const int B2 = 6;
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const int A3 = 7;
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const int B3 = 8;
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//output_ports
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const int S0 = 0;
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const int S1 = 1;
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const int S2 = 2;
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const int S3 = 3;
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#if USE_TWO_BIT_FULL_ADDER
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const int CO = 2;
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#else
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const int CO = 4;
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#endif
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}
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#include "basics.h"
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class one_bit_adder : public composite_node< tuple< signal_t, signal_t, signal_t >, tuple< signal_t, signal_t > > {
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broadcast_node<signal_t> A_port;
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broadcast_node<signal_t> B_port;
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broadcast_node<signal_t> CI_port;
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xor_gate<2> FirstXOR;
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xor_gate<2> SecondXOR;
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and_gate<2> FirstAND;
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and_gate<2> SecondAND;
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or_gate<2> FirstOR;
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graph& my_graph;
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typedef composite_node< tuple< signal_t, signal_t, signal_t >, tuple< signal_t, signal_t > > base_type;
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public:
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one_bit_adder(graph& g) : base_type(g), my_graph(g), A_port(g), B_port(g), CI_port(g), FirstXOR(g),
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SecondXOR(g), FirstAND(g), SecondAND(g), FirstOR(g) {
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make_connections();
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set_up_composite();
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}
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one_bit_adder(const one_bit_adder& src) :
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base_type(src.my_graph), my_graph(src.my_graph), A_port(src.my_graph), B_port(src.my_graph),
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CI_port(src.my_graph), FirstXOR(src.my_graph), SecondXOR(src.my_graph),
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FirstAND(src.my_graph), SecondAND(src.my_graph), FirstOR(src.my_graph)
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{
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make_connections();
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set_up_composite();
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}
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~one_bit_adder() {}
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private:
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void make_connections() {
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make_edge(A_port, input_port<0>(FirstXOR));
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make_edge(A_port, input_port<0>(FirstAND));
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make_edge(B_port, input_port<1>(FirstXOR));
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make_edge(B_port, input_port<1>(FirstAND));
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make_edge(CI_port, input_port<1>(SecondXOR));
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make_edge(CI_port, input_port<1>(SecondAND));
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make_edge(FirstXOR, input_port<0>(SecondXOR));
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make_edge(FirstXOR, input_port<0>(SecondAND));
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make_edge(SecondAND, input_port<0>(FirstOR));
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make_edge(FirstAND, input_port<1>(FirstOR));
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}
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void set_up_composite() {
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base_type::input_ports_type input_tuple(CI_port, A_port, B_port);
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base_type::output_ports_type output_tuple(output_port<0>(SecondXOR), output_port<0>(FirstOR));
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base_type::set_external_ports( input_tuple, output_tuple);
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base_type::add_visible_nodes(A_port, B_port, CI_port, FirstXOR, SecondXOR, FirstAND, SecondAND, FirstOR );
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}
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};
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#endif /* __TBBexample_graph_logicsim_oba_H */
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