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tbb/examples/parallel_reduce/convex_hull/readme.html
T
Hans Johnson e32d75f876 ENH: Update to TBB 2017 (2016-09-08 release)
The new release TBB is now under a new more
open license.
                                 Apache License
                           Version 2.0, January 2004
                        http://www.apache.org/licenses/

The list of most significant changes made over time in
Intel(R) Threading Building Blocks (Intel(R) TBB).

Intel TBB 2017
TBB_INTERFACE_VERSION == 9100

Changes (w.r.t. Intel TBB 4.4 Update 5):

- static_partitioner class is now a fully supported feature.
- async_node class is now a fully supported feature.
- Improved dynamic memory allocation replacement on Windows* OS to skip
    DLLs for which replacement cannot be done, instead of aborting.
- Intel TBB no longer performs dynamic memory allocation replacement
    for Microsoft* Visual Studio* 2008.
- For 64-bit platforms, quadrupled the worst-case limit on the amount
    of memory the Intel TBB allocator can handle.
- Added TBB_USE_GLIBCXX_VERSION macro to specify the version of GNU
    libstdc++ when it cannot be properly recognized, e.g. when used
    with Clang on Linux* OS. Inspired by a contribution from David A.
- Added graph/stereo example to demostrate tbb::flow::async_msg.
- Removed a few cases of excessive user data copying in the flow graph.
- Reworked split_node to eliminate unnecessary overheads.
- Added support for C++11 move semantics to the argument of
    tbb::parallel_do_feeder::add() method.
- Added C++11 move constructor and assignment operator to
    tbb::combinable template class.
- Added tbb::this_task_arena::max_concurrency() function and
    max_concurrency() method of class task_arena returning the maximal
    number of threads that can work inside an arena.
- Deprecated tbb::task_arena::current_thread_index() static method;
    use tbb::this_task_arena::current_thread_index() function instead.
- All examples for commercial version of library moved online:
    https://software.intel.com/en-us/product-code-samples. Examples are
    available as a standalone package or as a part of Intel(R) Parallel
    Studio XE or Intel(R) System Studio Online Samples packages.

Changes affecting backward compatibility:

- Renamed following methods and types in async_node class:
    Old                   New
    async_gateway_type => gateway_type
    async_gateway()    => gateway()
    async_try_put()    => try_put()
    async_reserve()    => reserve_wait()
    async_commit()     => release_wait()
- Internal layout of some flow graph nodes has changed; recompilation
    is recommended for all binaries that use the flow graph.

Preview Features:

- Added template class streaming_node to the flow graph API. It allows
    a flow graph to offload computations to other devices through
    streaming or offloading APIs.
- Template class opencl_node reimplemented as a specialization of
    streaming_node that works with OpenCL*.
- Added tbb::this_task_arena::isolate() function to isolate execution
    of a group of tasks or an algorithm from other tasks submitted
    to the scheduler.

Bugs fixed:

- Added a workaround for GCC bug #62258 in std::rethrow_exception()
    to prevent possible problems in case of exception propagation.
- Fixed parallel_scan to provide correct result if the initial value
    of an accumulator is not the operation identity value.
- Fixed a memory corruption in the memory allocator when it meets
    internal limits.
- Fixed the memory allocator on 64-bit platforms to align memory
    to 16 bytes by default for all allocations bigger than 8 bytes.
- As a workaround for crashes in the Intel TBB library compiled with
    GCC 6, added -flifetime-dse=1 to compilation options on Linux* OS.
- Fixed a race in the flow graph implementation.

Open-source contributions integrated:

- Enabling use of C++11 'override' keyword by Raf Schietekat.

------------------------------------------------------------------------
2016-09-28 21:12:48 +02:00

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<h1 class="title">Intel&reg; Threading Building Blocks.<br>Convex_hull sample</h1>
</div>
<p>
Parallel version of convex hull algorithm (quick hull).
</p>
<div class="changes">
<div class="h3-alike">System Requirements</div>
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<p>
For the most up to date system requirements, see the <a href="http://software.intel.com/en-us/articles/intel-threading-building-blocks-release-notes">release notes.</a>
</p>
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<div class="h3-alike">Files</div>
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<dl>
<dt><a href="convex_hull_sample.cpp">convex_hull_sample.cpp</a>
<dd>Source code for TBB version of example.
<dt><a href="convex_hull_bench.cpp">convex_hull_bench.cpp</a>
<dd>Source code for version of example that compares serial and TBB buffered and unbuffered implementations.
<dt><a href="convex_hull.h">convex_hull.h</a>
<dd>Include file for example.
<dt><a href="Makefile">Makefile</a>
<dd>Makefile for building the example.
</dl>
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<dl>
<dt><a href="msvs/">msvs</a>
<dd>Contains Microsoft* Visual Studio* workspace for building and running the example (Windows* systems only).
<dt><a href="xcode/">xcode</a>
<dd>Contains Xcode* IDE workspace for building and running the example (OS X* systems only).
</dl>
<p>For information about the minimum supported version of IDE, see <a href="http://software.intel.com/en-us/articles/intel-threading-building-blocks-release-notes">release notes.</a></p>
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<p>General build directions can be found <a href="../../index.html">here</a>.</p>
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<div class="h3-alike">Usage</div>
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<dl>
<dt><tt>convex_hull_sample [<i>S</i>] [<i>M</i>[:<i>N</i>]] [-v]</tt>
<dd><i>S</i> is the number of points (problem size).
<i>M:N</i> are a range of numbers of threads to be used.
Use the -v option to turn on verbose output.
<dt>To run a short version of this example, e.g., for use with Intel&reg; Threading Tools:
<dd>Build a <i>debug</i> version of the example
(see the <a href="../../index.html">build instructions</a>).
<br>Run it with a small problem size and the desired number of threads, e.g., <tt>convex_hull_sample&nbsp;500000&nbsp;4</tt>.
</dl>
</div>
</div>
<br>
<a href="../index.html">Up to parent directory</a>
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<p>
Intel and the Intel logo are trademarks of Intel Corporation in the U.S. and/or other countries.
<br>* Other names and brands may be claimed as the property of others.
<br>&copy; 2016, Intel Corporation
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