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Hans Johnson
e32d75f876
The new release TBB is now under a new more
open license.
Apache License
Version 2.0, January 2004
http://www.apache.org/licenses/
The list of most significant changes made over time in
Intel(R) Threading Building Blocks (Intel(R) TBB).
Intel TBB 2017
TBB_INTERFACE_VERSION == 9100
Changes (w.r.t. Intel TBB 4.4 Update 5):
- static_partitioner class is now a fully supported feature.
- async_node class is now a fully supported feature.
- Improved dynamic memory allocation replacement on Windows* OS to skip
DLLs for which replacement cannot be done, instead of aborting.
- Intel TBB no longer performs dynamic memory allocation replacement
for Microsoft* Visual Studio* 2008.
- For 64-bit platforms, quadrupled the worst-case limit on the amount
of memory the Intel TBB allocator can handle.
- Added TBB_USE_GLIBCXX_VERSION macro to specify the version of GNU
libstdc++ when it cannot be properly recognized, e.g. when used
with Clang on Linux* OS. Inspired by a contribution from David A.
- Added graph/stereo example to demostrate tbb::flow::async_msg.
- Removed a few cases of excessive user data copying in the flow graph.
- Reworked split_node to eliminate unnecessary overheads.
- Added support for C++11 move semantics to the argument of
tbb::parallel_do_feeder::add() method.
- Added C++11 move constructor and assignment operator to
tbb::combinable template class.
- Added tbb::this_task_arena::max_concurrency() function and
max_concurrency() method of class task_arena returning the maximal
number of threads that can work inside an arena.
- Deprecated tbb::task_arena::current_thread_index() static method;
use tbb::this_task_arena::current_thread_index() function instead.
- All examples for commercial version of library moved online:
https://software.intel.com/en-us/product-code-samples. Examples are
available as a standalone package or as a part of Intel(R) Parallel
Studio XE or Intel(R) System Studio Online Samples packages.
Changes affecting backward compatibility:
- Renamed following methods and types in async_node class:
Old New
async_gateway_type => gateway_type
async_gateway() => gateway()
async_try_put() => try_put()
async_reserve() => reserve_wait()
async_commit() => release_wait()
- Internal layout of some flow graph nodes has changed; recompilation
is recommended for all binaries that use the flow graph.
Preview Features:
- Added template class streaming_node to the flow graph API. It allows
a flow graph to offload computations to other devices through
streaming or offloading APIs.
- Template class opencl_node reimplemented as a specialization of
streaming_node that works with OpenCL*.
- Added tbb::this_task_arena::isolate() function to isolate execution
of a group of tasks or an algorithm from other tasks submitted
to the scheduler.
Bugs fixed:
- Added a workaround for GCC bug #62258 in std::rethrow_exception()
to prevent possible problems in case of exception propagation.
- Fixed parallel_scan to provide correct result if the initial value
of an accumulator is not the operation identity value.
- Fixed a memory corruption in the memory allocator when it meets
internal limits.
- Fixed the memory allocator on 64-bit platforms to align memory
to 16 bytes by default for all allocations bigger than 8 bytes.
- As a workaround for crashes in the Intel TBB library compiled with
GCC 6, added -flifetime-dse=1 to compilation options on Linux* OS.
- Fixed a race in the flow graph implementation.
Open-source contributions integrated:
- Enabling use of C++11 'override' keyword by Raf Schietekat.
------------------------------------------------------------------------
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<title>Intel® Threading Building Blocks. Polygon_overlay sample</title>
</head>
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<h1 class="title">Intel® Threading Building Blocks.<br>Polygon_overlay sample</h1>
</div>
<p>
Polygon Overlay example that demonstrates the use of parallel_for.
<br><br>
This example is a simple implementation of polygon overlay, as described in
<a href="http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.46.9538">
<i>Parallelizing the Polygon Overlay Problem Using Orca</i>, by H.F. Langendoen</a>.
<br><br>
The solution was implemented in three forms:
<ul>
<li>The naive serial solution.
<li>The naive parallel solution, by splitting list of polygons from one map and intersecting
each sub-list against the entire list of polygons from the second map.
<li>A parallel solution where each map is split into submaps, with each resulting submap being
intersected against the corresponding submap from the other map. This solution requires some
redundancy (some polygons are members of more than one submap). To prevent multiple copies
of a polygon from being placed in the solution map, if both polygons are duplicated (that is,
if they both appear in more than one map), they are intersected but the result is not placed
in the solution map.
</ul>
The only optimization in each solution is that the area of the generated sub-polygons are subtracted from
the original area of one of the source polygons. When the remaining area is zero, the intersection process
is halted.
<br><br>
<i>A word about the speedup of the submap case.</i> One may get superlinear speedup in this case (for instance a
laptop with Intel® Core(TM) Duo processor got a speedup of about 20 percent over serial.) This results from two effects:
<ul>
<li>the number of threads used, and
<li>the fact that for each submap, the number of polygons is smaller than that for the other two cases.
</ul>
If there are, say, 400 polygons in each map, then on average the number of intersections calculated is
approximately 80,000 (400 * 200, where 200 is the average number of polygons examined before stopping.)
If the maps are split into 2 submaps, the time for each submap is about 200*100, or 20,000. So even
comparing the two sets of submaps serially should result in a speedup somewhere around 2. This number
is affected by the number of redundant polygons being compared; this effect would eventually swamp the gain
from comparing smaller numbers of polygons per submap. And remember the submaps are created by intersecting each
map with a rectangular polygon covering the submap being generated, which is additional work taking about N * O(400)
in the case above, where N is the number of submaps generated, that can be done in parallel.
<br><br>
Running the default release pover while varying the number of submaps from 1 to 1000, the speedup on the submap
case for a 2-processor system looks like
<br><br>
<img src="speedup.gif" alt="Table of speedup for the algorithm">
<br><br>
One further optimization would be to sort one map, say <b>map1</b>, by maxY, and sort the other map (<b>map2</b>)
by minY. For <b>p1</b> in <b>map1</b>, start testing for intersection at the first <b>p2</b> in <b>map2</b>
that intersected the last polygon tested in <b>map1</b>. This would speed up the intersection process greatly,
but the optimization would apply to all the methods, and the sort would have to be accounted for in the timing.
<br><br>
The source maps are generated pseudo-randomly in the manner described in the paper above. That is, if
we need N polygons, then N "boxes" are chosen at random, then one-at-a-time the areas are expanded in
one of fours directions until the area hits an adjacent polygon. When this process is finished, the
resulting map is inspected and any remaining unoccupied "boxes" are made into additional polygons, as
large as possible in each case. So the actual number of polygons in each map will in general be larger
than the number of polygons requested (sometimes by 10% or more.)
<br><br>
One limitation of the program is that if the number of polygons in the source map is greater than the number of
"boxes" (pixels in the GUI case), the maps cannot be generated.
</p>
<div class="changes">
<div class="h3-alike">System Requirements</div>
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<p>
For the most up to date system requirements, see the <a href="http://software.intel.com/en-us/articles/intel-threading-building-blocks-release-notes">release notes.</a>
</p>
</div>
</div>
<div class="changes">
<div class="h3-alike">Files</div>
<input type="checkbox" checked="checked">
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<dl>
<dt><a href="polyover.cpp">polyover.cpp</a>
<dd>Source code for main program.
<dt><a href="polyover.h">polyover.h</a>
<dd>Global variables, classes and enums.
<dt><a href="pover_video.cpp">pover_video.cpp</a>
<dd>Source code for the GUI interface.
<dt><a href="pover_video.h">pover_video.h</a>
<dd>Defines for the GUI version.
<dt><a href="Makefile">Makefile</a>
<dd>Makefile for building the example.
</dl>
</div>
</div>
<div class="changes">
<div class="h3-alike">Directories</div>
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<dl>
<dt><a href="msvs/">msvs</a>
<dd>Contains Microsoft* Visual Studio* workspace for building and running the example (Windows* systems only).
<dt><a href="xcode/">xcode</a>
<dd>Contains Xcode* IDE workspace for building and running the example (OS X* systems only).
</dl>
<p>For information about the minimum supported version of IDE, see <a href="http://software.intel.com/en-us/articles/intel-threading-building-blocks-release-notes">release notes.</a></p>
</div>
</div>
<div class="changes">
<div class="h3-alike">Build instructions</div>
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<p>
General build directions can be found <a href="../../index.html">here</a>.
<br><br>
For the various UI options, see the <a href="../../common/index.html">common GUI code</a> build instructions.
</p>
</div>
</div>
<div class="changes">
<div class="h3-alike">Usage</div>
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<p>
Building via the above make commands, or via Microsoft* Visual Studio* projects on Windows* systems, produces executable files
named pover.exe. To run these executables directly, use one or more of the following commands:
</p>
<dl>
<dt><tt>pover.exe</tt>
<dd>Run this version (release or debug).
<dt><tt>pover.exe n:m</tt>
<dd>Run this version (release or debug) (m-n+1) times, with n threads to m threads inclusive.
<dt>To run a short version of this example, e.g., for use with Intel® Threading Tools:
<dd>Build a <i>debug</i> version with the GUI turned off
(e.g., <tt>make UI=con debug</tt>; see also the build directions above).
<br>Run it with a small dataset, e.g., <tt>pover.exe --polys 10 --size 5x5</tt>.
</dl>
</div>
</div>
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<div class="h3-alike">Notes</div>
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<ul>
<li>While running with the GUI display should yield reasonable performance in most cases, <i>running with no GUI
display is strongly recommended</i> in order to demonstrate the full performance and scalability of the example.
</ul>
</div>
</div>
<br>
<a href="../index.html">Up to parent directory</a>
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<p>
Intel, Intel Core and the Intel logo are trademarks of Intel Corporation in the U.S. and/or other countries.
<br>* Other names and brands may be claimed as the property of others.
<br>© 2016, Intel Corporation
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