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https://github.com/wjakob/tbb.git
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Pau Argelaguet
59 lines
2.4 KiB
C++
59 lines
2.4 KiB
C++
/*
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Copyright (c) 2005-2019 Intel Corporation
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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#ifndef __TBBexample_graph_logicsim_fba_H
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#define __TBBexample_graph_logicsim_fba_H 1
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#include "one_bit_adder.h"
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typedef composite_node< tuple< signal_t, signal_t, signal_t, signal_t, signal_t, signal_t, signal_t, signal_t, signal_t >,
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tuple< signal_t, signal_t, signal_t, signal_t, signal_t > > fba_base_type;
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class four_bit_adder : public fba_base_type {
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graph& my_graph;
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std::vector<one_bit_adder> four_adders;
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public:
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four_bit_adder(graph& g) : fba_base_type(g), my_graph(g), four_adders(4, one_bit_adder(g)) {
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make_connections();
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set_up_composite();
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}
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four_bit_adder(const four_bit_adder& src) :
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fba_base_type(src.my_graph), my_graph(src.my_graph), four_adders(4, one_bit_adder(src.my_graph))
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{
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make_connections();
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set_up_composite();
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}
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~four_bit_adder() {}
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private:
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void make_connections() {
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make_edge(output_port<1>(four_adders[0]), input_port<0>(four_adders[1]));
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make_edge(output_port<1>(four_adders[1]), input_port<0>(four_adders[2]));
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make_edge(output_port<1>(four_adders[2]), input_port<0>(four_adders[3]));
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}
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void set_up_composite() {
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fba_base_type::input_ports_type input_tuple(input_port<0>(four_adders[0]/*CI*/), input_port<1>(four_adders[0]), input_port<2>(four_adders[0]), input_port<1>(four_adders[1]), input_port<2>(four_adders[1]), input_port<1>(four_adders[2]), input_port<2>(four_adders[2]), input_port<1>(four_adders[3]), input_port<2>(four_adders[3]));
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fba_base_type::output_ports_type output_tuple(output_port<0>(four_adders[0]), output_port<0>(four_adders[1]), output_port<0>(four_adders[2]), output_port<0>(four_adders[3]),output_port<1>(four_adders[3]/*CO*/));
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fba_base_type::set_external_ports(input_tuple, output_tuple);
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}
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};
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#endif /* __TBBexample_graph_logicsim_fba_H */
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