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Wenzel Jakob
61 lines
2.9 KiB
C++
61 lines
2.9 KiB
C++
/*
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Copyright 2005-2016 Intel Corporation. All Rights Reserved.
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This file is part of Threading Building Blocks. Threading Building Blocks is free software;
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you can redistribute it and/or modify it under the terms of the GNU General Public License
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version 2 as published by the Free Software Foundation. Threading Building Blocks is
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distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the
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implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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See the GNU General Public License for more details. You should have received a copy of
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the GNU General Public License along with Threading Building Blocks; if not, write to the
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Free Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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As a special exception, you may use this file as part of a free software library without
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restriction. Specifically, if other files instantiate templates or use macros or inline
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functions from this file, or you compile this file and link it with other files to produce
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an executable, this file does not by itself cause the resulting executable to be covered
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by the GNU General Public License. This exception does not however invalidate any other
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reasons why the executable file might be covered by the GNU General Public License.
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*/
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#ifndef __TBBexample_graph_logicsim_dlatch_H
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#define __TBBexample_graph_logicsim_dlatch_H 1
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#include "basics.h"
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class D_latch : public composite_node< tuple< signal_t, signal_t >, tuple< signal_t, signal_t > > {
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broadcast_node<signal_t> D_port;
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broadcast_node<signal_t> E_port;
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not_gate a_not;
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and_gate<2> first_and;
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and_gate<2> second_and;
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nor_gate<2> first_nor;
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nor_gate<2> second_nor;
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graph& my_graph;
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typedef composite_node< tuple< signal_t, signal_t >, tuple< signal_t, signal_t > > base_type;
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public:
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D_latch(graph& g) : base_type(g), my_graph(g), D_port(g), E_port(g), a_not(g), first_and(g), second_and(g),
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first_nor(g), second_nor(g)
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{
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make_edge(D_port, input_port<0>(a_not));
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make_edge(D_port, input_port<1>(second_and));
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make_edge(E_port, input_port<1>(first_and));
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make_edge(E_port, input_port<0>(second_and));
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make_edge(a_not, input_port<0>(first_and));
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make_edge(first_and, input_port<0>(first_nor));
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make_edge(second_and, input_port<1>(second_nor));
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make_edge(first_nor, input_port<0>(second_nor));
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make_edge(second_nor, input_port<1>(first_nor));
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base_type::input_ports_type input_tuple(D_port, E_port);
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base_type::output_ports_type output_tuple(output_port<0>(first_nor), output_port<0>(second_nor));
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base_type::set_external_ports(input_tuple, output_tuple);
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base_type::add_visible_nodes(D_port, E_port, a_not, first_and, second_and, first_nor, second_nor);
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}
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~D_latch() {}
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};
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#endif /* __TBBexample_graph_logicsim_dlatch_H */
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